A Design- for-Diagnosis Technique for Diagnosing Integrated Circuit Faults with Faulty Scan Chains

1 This paper is supported in part by National Natural Science Foundation of China (NSFC) under grant No.(60633060), and in part by National Basic Research Program of China (973) under grant No.(2005CB321604). Abstract Scan chains take as much as 30% of the silicon area [1], while scan chain failure accounts for almost 50% of chip failure [2]. Conventional logic diagnosis techniques abort the diagnostic procedure after diagnosing the faulty scan chains, leaving large failure area to time-consuming failure analysis methods such as optical microscopy and FIB (focused ion beam). In this paper, a design-fordiagnosis (DFD) technique is proposed to not only diagnose faulty scan chains precisely and efficiently but also diagnose the whole chip with faulty scan chains. The proposed approach is entirely compatible with conventional scan-based design. Previously proposed software-based diagnostic methods for conventional scan designs can be applied to our design without modification. Experiments on the ISCAS'89 benchmark circuits are conducted to demonstrate the efficiency of the proposed DFD technique.